Infineon Technologies

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Posted by r2d2 04/19/2009 @ 06:07

Tags : infineon technologies, semi conductors, technology

News headlines
Infineon, Indian researchers claim ESD advance - EE Times Deutschland
BANGALORE, India — A joint research team from Infineon Technologies and the Indian Institute of Technology, Bombay, is claiming an advance in the integration of high-voltage functionality for advanced CMOS technologies. The joint program, launched in...
Wi-Lan Buys Patents To Boost Wireless Program >WIN.T - Wall Street Journal
By Jennifer Walter The Ottawa technology innovation and licensing company settled patent litigation with Infineon Technologies AG (IFX.XE) and also purchased more than 200 patents from Infineon, Airspan Networks Inc. (AIRN) and Technology Research...
DJ DGAP-Adhoc: Infineon Technologies AG: INFINEON LAUNCHES ... - Märkische Allgemeine
The Bonds will of Infineon, and will be guaranteed by Infineon. The Bonds will be marketed to institutional investors by way of an accelerated bookbuilding. The strategy. The Bonds will strengthen Infineon's liquidity position and launch until the time...
PRESS RELEASE: Infineon: Results Of The Bond Tender Offer - Wall Street Journal
Infineon Technologies AG / Miscellaneous 11.05.2009 Release of an Ad hoc announcement according to ?? 15 WpHG, transmitted by DGAP - a company of EquityStory AG. The issuer is solely responsible for the content of this announcement....
Infineon 150 mln euro debt buyback plan buoys shares - Forbes
By Daisy Ku LONDON, May 5 (Reuters) - Infineon Technologies ( IFX - news - people ) shares jumped over 13 percent after the German chipmaker said on Tuesday it would cut its debt by buying back up to 150 million euros ($201 million) worth of...
Infineon, ST led the industrial chip market in 2008, says analyst - EE Times Deutschland
The industrial semiconductor market does not have a single dominant supplier but Infineon Technologies AG and STMicroelectronics NV competed for the position of largest supplier in 2008. With less than one percentage point of market share between them,...
SolarBridge Seeks Up to $15M, Launches Microinverters in 4Q - Greentech Media
He was the CEO of Primarion, a power management chip developer, before it was sold to Infineon Technologies in April last year. Inverters play a central role in the workings of a solar energy system. They convert the direct current produced by the...
Infineon Technologies AG - SWOT Analysis - ... - (Pressemitteilung)
This Infineon Technologies AG - SWOT Analysis company profile is the essential source for top-level company data and information. The report examines the company's key business structure and operations, history and products, and provides summary...
Infineon Technologies Joins ARM Connected Community - IQ Online
Infineon Technologies AG, headquartered in Germany and specialising in designing, making and supplying a range of semiconductors used in microelectronics applications, has joined the ARM Connected Community. As part of the ARM Connected Community,...
Infineon Technologies: JP Morgan passe à surpondérer -
Financing options have increased: The aggressive cost-cutting plan, improving revenue in wireless & stabilisation in automotive demand (though no real improvement), have resulted in a higher cash expectation at the end of June 2010 when Infineon will...

Infineon Technologies


Infineon Technologies AG (FWB: IFX, NYSE: IFX) was founded in April 1999 when the semiconductor operations of parent company, Siemens AG, were spun off to form a separate legal entity. As of September 30, 2007 Infineon has about 43,000 employees worldwide, 6000 of them involved in research and development. In the 2007 financial year, the company achieved sales of US$11.66 billion. In 2007 a 14.6% rise in projected calendar year revenues saw Infineon taking 10th place in iSuppli's global semiconductor sales ranking, thus gaining five places from 2006.

On May 1, 2006, Infineon's Memory Products division was carved out as a distinct company called Qimonda AG. It employs about 13,500 people worldwide. Qimonda was listed on the New York Stock Exchange until 2009.

Infineon Technologies AG, Neubiberg near Munich, Germany, offers semiconductor and system solutions for automotive, industrial and multimarket sectors, for applications in communication, as well as memory products through its subsidiary Qimonda. With a global presence, Infineon operates through its subsidiaries in the USA from Milpitas, California in the Asia-Pacific region from Singapore and in Japan from Tokyo.

Infineon has a number of facilities in Europe. Infineon's high power segment is in Warstein (Germany), Villach (Austria) and Cegléd (Hungary) and Italy. It also runs R&D centers in France, Singapore, Romania, Taiwan & Banglore, India & fabrication units in Singapore, Malaysia, Indonesia & China.

Infineon is listed in the TecDAX index of the Frankfurt Stock Exchange, having been a DAX constituent between June 2000 and March 2009, and on the New York Stock Exchange.

Infineon also has an HPS (High Power Segment). The front-end of this production is in Warstein (GER), the back-end is in Cegléd (Hungary). Thyristors, diodes and IGBTs are manufactured here.

During the 2008 Olympic Games in Beijng in August, Chinese automobile manufacturer Chang'an Motors will supply a number of hybrid-drive cars as taxis for the athletes and spectators. The power electronics for the "mild hybrid" drive (HybridPACK 1) will be supplied by Infineon..

Major institutional investors in Infineon are: Dodge and Cox International: 10.03%, Merrill Lynch International: 5.25%, Templeton Global Advisors Limited: 5.16%, Capital Group International: 4.14%.

In 2004–2005 an investigation was carried out into a worldwide DRAM price fixing conspiracy during 1999–2002 that damaged competition and raised PC prices. As a result, Samsung is to pay $300 million fine, Hynix was to pay $185 million in 2005, Infineon: $160 million in 2004. Micron Technology cooperated with prosecutors and no fine is expected.

AENEON was introduced in 2005. AENEON is a DRAM memory family of Infineon and fits into standard PCs and notebooks.

AENEON targets whitebox (non-brand) PC and notebook manufacturers world wide, as well as the European retail segment and end users (web shop). AENEON DRAM memory focuses the "price-performance" segment.

Price advantages are obtained due to a limited product portfolio (only unbuffered and SO-DIMM), and due to outsourced module assembly. The DRAM components, however, are "Made by Infineon".

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Intel 8051

Intel P8051 microcontroller.

The Intel 8051 is a Harvard architecture, single chip microcontroller (µC) which was developed by Intel in 1980 for use in embedded systems. Intel's original versions were popular in the 1980s and early 1990s, but has today largely been superseded by a vast range of faster and/or functionally enhanced 8051-compatible devices manufactured by more than 20 independent manufacturers including Atmel, Infineon Technologies (formerly Siemens AG), Maxim Integrated Products (via its Dallas Semiconductor subsidiary), NXP (formerly Philips Semiconductor), Nuvoton (formerly Winbond), ST Microelectronics, Silicon Laboratories (formerly Cygnal), Texas Instruments and Cypress Semiconductor. Intel's official designation for the 8051 family of µCs is MCS 51.

Intel's original 8051 family was developed using NMOS technology, but later versions, identified by a letter "C" in their name, e.g. 80C51, used CMOS technology and were less power-hungry than their NMOS predecessors. This made them more suitable for battery-powered devices.

A particularly useful feature of the 8051 core is the inclusion of a boolean processing engine which allows bit-level boolean logic operations to be carried out directly and efficiently on internal registers and RAM. This feature helped to cement the 8051's popularity in industrial control applications. Another valued feature is that it has four separate register sets, which can be used to greatly reduce interrupt latency compared to the more common method of storing interrupt context on a stack.

The 8051 UARTs make it simple to use the chip as a serial communications interface. External pins can be configured to connect to internal shift registers in a variety of ways, and the internal timers can also be used, allowing serial communications in a number of modes, both synchronous and asynchronous. Some modes allow communications with no external components. A mode compatible with an RS-485 multi-point communications environment is achievable, but the 8051's real strength is fitting in with existing ad-hoc protocols, e.g when controlling serial-controlled devices.

Once a UART - and a timer, if necessary, have been configured, the programmer needs only to write a simple interrupt routine to refill the 'send' shift register whenever the last bit is shifted out by the UART and/or empty the full 'receive' shift register (copy the data somewhere else). The main program then performs serial reads and writes simply by reading and writing 8-bit data to stacks.

8051 based microcontrollers typically include one or two UARTs, two or three timers, 128 or 256 bytes of internal data RAM (16 bytes of which are bit-addressable), up to 128 bytes of I/O, 512 bytes to 64 kB of internal program memory, and sometimes a quantity of extended data RAM (ERAM) located in the external data space. The original 8051 core ran at 12 clock cycles per machine cycle, with most instructions executing in one or two machine cycles. With a 12 MHz clock frequency, the 8051 could thus execute 1 million one-cycle instructions per second or 500,000 two-cycle instructions per second. Enhanced 8051 cores are now commonly used which run at six, four, two, or even one clock per machine cycle, and have clock frequencies of up to 100 MHz, and are thus capable of an even greater number of instructions per second. All SILabs, some Dallas and a few Atmel devices have single cycle cores.

Even higher speed single cycle 8051 cores, in the range 130 MHz to 150 MHz, are now available in internet downloadable form for use in programmable logic devices such as FPGAs, and at many hundreds of MHz in ASICs, for example the netlist from

Common features included in modern 8051 based microcontrollers include built-in reset timers with brown-out detection, on-chip oscillators, self-programmable Flash ROM program memory, bootloader code in ROM, EEPROM non-volatile data storage, I²C, SPI, and USB host interfaces, PWM generators, analog comparators, A/D and D/A converters, RTCs, extra counters and timers, in-circuit debugging facilities, more interrupt sources, and extra power saving modes.

Several C compilers are available for the 8051, most of which feature extensions that allow the programmer to specify where each variable should be stored in its six types of memory, and provide access to 8051 specific hardware features such as the multiple register banks and bit manipulation instructions. Other high level languages such as Forth, BASIC, Pascal/Object Pascal, PL/M and Modula 2 are available for the 8051, but they are less widely used than C and assembly.

The 8051's predecessor, the 8048, was used in the keyboard of the first IBM PC, where it converted keypresses into the serial data stream which is sent to the main unit of the computer. The 8048 and derivatives are still used today for basic model keyboards.

The 8031 was a cut down version of the original Intel 8051 that did not contain any internal program memory (ROM). To use this chip external ROM had to be added containing the program that the 8031 would fetch and execute.

The 8052 was an enhanced version of the original 8051 that featured 256 bytes of internal RAM instead of 128 bytes, 8 kB of ROM instead of 4 kB, and a third 16-bit timer. The 8032 had these same features except for the internal ROM program memory. The 8052 and 8032 are largely considered to be obsolete because these features and more are included in nearly all modern 8051 based microcontrollers.

This article was originally based on material from the Free On-line Dictionary of Computing, which is licensed under the GFDL.

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MIPS architecture

A MIPS R4400 microprocessor made by Toshiba.

MIPS (originally an acronym for Microprocessor without Interlocked Pipeline Stages) is a reduced Instruction set computing (RISC) instruction set architecture (ISA) developed by MIPS Computer Systems (now MIPS Technologies). In the mid to late 1990s, it was estimated that one in three RISC microprocessors produced were MIPS implementations.

MIPS implementations are currently primarily used in many embedded systems such as the Series2 TiVo, Windows CE devices, Cisco routers, residential gateways, Foneras, Avaya, and video game consoles like the Nintendo 64 and Sony PlayStation, PlayStation 2, and PlayStation Portable handheld system. Until late 2006 they were also used in many of SGI's computer products. MIPS implementations were also used by Digital Equipment Corporation, NEC, Pyramid Technology, Siemens Nixdorf, Tandem and others during the late 1980s and 1990s.

The early MIPS architectures were 32-bit (generally 32-bit wide registers and data paths), while later versions were 64-bit. Multiple revisions of the MIPS instruction set exist, including MIPS I, MIPS II, MIPS III, MIPS IV, MIPS V, MIPS32, and MIPS64. The current revisions are MIPS32 (for 32-bit implementations) and MIPS64 (for 64-bit implementations). MIPS32 and MIPS64 define a control register set as well as the instruction set. Several "add-on" extensions are also available, including MIPS-3D which is a simple set of floating-point SIMD instructions dedicated to common 3D tasks, MDMX (MaDMaX) which is a more extensive integer SIMD instruction set using the 64-bit floating-point registers, MIPS16e which adds compression to the instruction stream to make programs take up less room (allegedly a response to the Thumb encoding in the ARM architecture), and the recent addition of MIPS MT, new multithreading additions to the system similar to HyperThreading in the Intel's Pentium 4 processors.

Computer architecture courses in universities and technical schools often study the MIPS architecture. The architecture greatly influenced later RISC architectures such as Alpha (previously Alpha AXP).

In 1981, a team led by John L. Hennessy at Stanford University started work on what would become the first MIPS processor. The basic concept was to increase performance through the use of deep instruction pipelines. Pipelining as a basic technique was well known before (see IBM 801 for instance), but not developed into its full potential. CPUs are built up from a number of dedicated sub-units such as instruction decoders, ALUs (integer arithmetics and logic), load/store units (handling memory), and so on. In a traditional non-optimized design, a particular instruction in a program sequence must be (almost) completed before the next can start to "flow" from one unit to another; in a pipelined architecture, successive instructions instead overlaps in execution. For instance, at the same time a math instruction is fed into the floating point unit, the load/store unit can fetch the next instruction.

One major barrier to pipelining was that some instructions, like division, take longer to complete and the CPU therefore has to wait before passing the next instruction into the pipeline. One solution to this problem is to use a series of interlocks that allows stages to indicate that they are busy, pausing the other stages upstream. Hennessy's team viewed these interlocks as a major performance barrier since they had to communicate to all the modules in the CPU which takes time, and appeared to limit the clock speed. A major aspect of the MIPS design was to fit every sub-phase, including cache-access, of all instructions into one cycle, thereby removing any needs for interlocking, and permitting a single cycle throughput.

Although this design eliminated a number of useful instructions such as multiply and divide it was felt that the overall performance of the system would be dramatically improved because the chips could run at much higher clock rates. This ramping of the speed would be difficult with interlocking involved, as the time needed to set up locks is as much a function of die size as clock rate. The elimination of these instructions became a contentious point.

The other difference between the MIPS design and the competing Berkeley RISC involved the handling of subroutine calls. RISC used a technique called register windows to improve performance of these very common tasks, but this limited the maximum depth of multi-level calls. Each subroutine call required its own set of registers, which in turn required more real estate on the CPU and more complexity in its design. Hennessy felt that a careful compiler could find free registers without resorting to a hardware implementation, and that simply increasing the number of registers would not only make this simple, but increase the performance of all tasks.

In other ways the MIPS design was very much a typical RISC design. To save bits in the instruction word, RISC designs reduce the number of instructions to encode. The MIPS design uses 6 bits of the 32-bit word for the basic opcode; the rest may contain a single 26-bit jump address or it may have up to four 5-bit fields specifying up to three registers plus a shift value combined with another 6-bits of opcode; another format, among several, specifies two registers combined with a 16-bit immediate value, etc. This allowed this CPU to load up the instruction and the data it needed in a single cycle, whereas an (older) non-RISC design, such as the MOS Technology 6502 for instance, required separate cycles to load the opcode and the data. This was one of the major performance improvements that RISC offered. However, modern non-RISC designs achieves this speed by other means (such as queues in the CPU).

In 1984 Hennessy was convinced of the future commercial potential of the design, and left Stanford to form MIPS Computer Systems. They released their first design, the R2000, in 1985, improving the design as the R3000 in 1988. These 32-bit CPUs formed the basis of their company through the 1980s, used primarily in SGI's series of workstations. These commercial designs deviated from the Stanford academic research by implementing most of the interlocks in hardware, supplying full multiply and divide instructions (among others).

In the early 1990s MIPS started licensing their designs to third-party vendors. This proved fairly successful due to the simplicity of the core, which allowed it to be used in a number of applications that would have formerly used much less capable CISC designs of similar gate count and price -- the two are strongly related; the price of a CPU is generally related to the number of gates and the number of external pins. Sun Microsystems attempted to enjoy similar success by licensing their SPARC core but was not nearly as successful. By the late 1990s MIPS was a powerhouse in the embedded processor field, and in 1997 the 48-millionth MIPS-based CPU shipped, making it the first RISC CPU to outship the famous 68k family. MIPS was so successful that SGI spun-off MIPS Technologies in 1998. Fully half of MIPS' income today comes from licensing their designs, while much of the rest comes from contract design work on cores that will then be produced by third parties.

In 1999 MIPS formalized their licensing system around two basic designs, the 32-bit MIPS32 (based on MIPS II with some additional features from MIPS III, MIPS IV, and MIPS V) and the 64-bit MIPS64 (based on MIPS V). NEC, Toshiba and SiByte (later acquired by Broadcom) each obtained licenses for the MIPS64 as soon as it was announced. Philips, LSI Logic and IDT have since joined them. Success followed success, and today the MIPS cores are one of the most-used "heavyweight" cores in the marketplace for computer-like devices (hand-held computers, set-top boxes, etc.), with other designers fighting it out for other niches. Some indication of their success is the fact that Freescale (spun-off by Motorola) uses MIPS cores in their set-top box designs, instead of their own PowerPC-based cores.

Since the MIPS architecture is licensable, it has attracted several processor start-up companies over the years. One of the first start-ups to design MIPS processors was Quantum Effect Devices (see next section). The MIPS design team that designed the R4300 started the company SandCraft, which designed the R5432 for NEC and later produced the SR71000, one of the first out-of-order execution processors for the embedded market. The original DEC StrongARM team eventually split into two MIPS-based start-ups: SiByte which produced the SB-1250, one of the first high-performance MIPS-based systems-on-a-chip (SOC); while Alchemy Semiconductor (later acquired by AMD) produced the Au-1000 SoC for low-power applications. Lexra used a MIPS-like architecture and added DSP extensions for the audio chip market and multithreading support for the networking market. Due to Lexra not licensing the architecture, two lawsuits were started between the two companies. The first was quickly resolved when Lexra promised not to advertise their processors as MIPS-compatible. The second (about MIPS patent 4814976 for handling unaligned memory access) was protracted, hurt both companies' business, and culminated in MIPS Technologies giving Lexra a free license and a large cash payment.

Two companies have emerged that specialize in building multi-core devices using the MIPS architecture. Raza Microelectronics, Inc. purchased the product line from failing SandCraft and later produced devices that contained eight cores that were targeted at the telecommunications and networking markets. Cavium Networks, originally a security processor vendor also produced devices with eight CPU cores for the same markets. Both of these companies designed their cores in-house, just licensing the architecture instead of purchasing cores from MIPS.

Among the manufacturers which have made computer workstation systems using MIPS processors are SGI, MIPS Computer Systems, Inc., Whitechapel Workstations, Olivetti, Siemens-Nixdorf, Acer, Digital Equipment Corporation, NEC, and DeskStation. Operating systems ported to the architecture include SGI's IRIX, Microsoft's Windows NT (until v4.0), Windows CE, Linux, BSD, UNIX System V, SINIX and MIPS Computer Systems' own RISC/os.

There was speculation in the early 1990s that MIPS and other powerful RISC processors would overtake the Intel IA32 architecture. This was encouraged by the support of the first two versions of Microsoft's Windows NT for DEC Alpha, MIPS and PowerPC - and to a lesser extent the Clipper architecture and SPARC. However, as Intel quickly released faster versions of their Pentium class CPUs, Microsoft Windows NT v4.0 dropped support for anything but Intel and Alpha. With SGI's decision to transition to the Itanium and IA32 architectures, use of MIPS processors on the desktop has now disappeared almost completely.

See main article Advanced Computing Environment.

Through the 1990s, the MIPS architecture was widely adopted by the embedded market, including for use in computer networking/telecommunications, video arcade games, home video game consoles, computer printers, digital set-top boxes, digital televisions, DSL and cable modems, and personal digital assistants.

The low power-consumption and heat characteristics of embedded MIPS implementations, the wide availability of embedded development tools, and knowledge about the architecture means use of MIPS microprocessors in embedded roles is likely to remain common.

In recent years most of the technology used in the various MIPS generations has been offered as IP-cores (building-blocks) for embedded processor designs. Both 32-bit and 64-bit basic cores are offered, known as the 4K and 5K respectively, and the design itself can be licensed as MIPS32 and MIPS64. These cores can be mixed with add-in units such as FPUs, SIMD systems, various input/output devices, etc.

MIPS cores have been commercially successful, now being used in many consumer and industrial applications. MIPS cores can be found in newer Cisco, Linksys and Mikrotik's routerboard routers, cable modems and ADSL modems, smartcards, laser printer engines, set-top boxes, robots, handheld computers, Sony PlayStation 2 and Sony PlayStation Portable. In cellphone/PDA applications, the MIPS core has been unable to displace the incumbent, competing ARM core.

MIPS architecture processors include: IDT RC32438; ATI Xilleon; Alchemy Au1000, 1100, 1200; Broadcom Sentry5; RMI XLR7xx, Cavium Octeon CN30xx, CN31xx, CN36xx, CN38xx and CN5xxx; Infineon Technologies EasyPort, Amazon, Danube, ADM5120, WildPass, INCA-IP, INCA-IP2; NEC EMMA and EMMA2, NEC VR4181A, VR4121, VR4122, VR4181A, VR5432, VR5500; Oak Technologies Generation; PMC-Sierra RM11200; QuickLogic QuickMIPS ESP; Toshiba "Donau", Toshiba TMPR492x, TX4925, TX9956, TX7901.

One of the more interesting applications of the MIPS architecture is its use in massive processor count supercomputers. Silicon Graphics (SGI) refocused its business from desktop graphics workstations to the high performance computing (HPC) market in the early 1990s. The success of the company's first foray into server systems, the Challenge series based on the R4400 and R8000, and later R10000, motivated SGI to create a vastly more powerful system. The introduction of the integrated R10000 allowed SGI to produce a system, the Origin 2000, eventually scalable to 1024 CPUs using its NUMAlink cc-NUMA interconnect. The Origin 2000 begat the Origin 3000 series which topped out with the same 1024 maximum CPU count but using the R14000 and R16000 chips up to 700 MHz. Its MIPS based supercomputers were withdrawn in 2005 when SGI made the strategic decision to move to Intel's IA-64 architecture.

An HPC startup introduced a radical MIPS based supercomputer in 2007. SiCortex, Inc. has created a tightly integrated Linux cluster supercomputer based on the MIPS64 architecture and a high performance interconnect based on the Kautz digraph topology. The system is very power efficient and computationally powerful. The most unique aspect of the system is its multicore processing node which integrates six MIPS64 cores, a crossbar memory controller, interconnect DMA engine, Gigabit Ethernet and PCI Express controllers all on a single chip which consumes only 10 watts of power, yet has a peak floating point performance of 6 GFLOPs. The most powerful configuration, the SC5832, is a single cabinet supercomputer consisting of 972 such node chips for a total of 5832 MIPS64 processor cores and 8.2 teraFLOPS of peak performance.

The first commercial MIPS CPU model, the R2000, was announced in 1985. It added multiple-cycle multiply and divide instructions in a somewhat independent on-chip unit. New instructions were added to retrieve the results from this unit back to the execution core; these result-retrieving instructions were interlocked.

The R2000 could be booted either big-endian or little-endian. It had thirty-two 32-bit general purpose registers, but no condition code register (the designers considered it a potential bottleneck), a feature it shares with the AMD 29000 and the Alpha. Unlike other registers, the program counter is not directly accessible.

The R2000 also had support for up to four co-processors, one of which was built into the main CPU and handled exceptions, traps and memory management, while the other three were left for other uses. One of these could be filled by the optional R2010 FPU, which had thirty-two 32-bit registers that could be used as sixteen 64-bit registers for double-precision.

The R3000 succeeded the R2000 in 1988, adding 32 KB (soon increased to 64 KB) caches for instructions and data, along with cache coherency support for multiprocessor use. While there were flaws in the R3000's multiprocessor support, it still managed to be a part of several successful multiprocessor designs. The R3000 also included a built-in MMU, a common feature on CPUs of the era. The R3000, like the R2000, could be paired with a R3010 FPU. The R3000 was the first successful MIPS design in the marketplace, and eventually over one million were made. A speed-bumped version of the R3000 running up to 40 MHz, the R3000A delivered a performance of 32 VUPs (VAX Unit of Performance). The R3000A was the processor used in the extremely successful Sony PlayStation. Third-party designs include Performance Semiconductor's R3400 and IDT's R3500, both of them were R3000As with an integrated R3010 FPU. Toshiba's R3900 was a virtually first SoC for the early handheld PCs based on the Windows CE. A radiation-hardened variant for space applications, the Mongoose-V, is a R3000 with an integrated R3010 FPU.

The R4000 series, released in 1991, extended the MIPS instruction set to a full 64-bit architecture, moved the FPU onto the main die to create a single-chip microprocessor, and operated at a radically high internal clock speed (it was introduced at 100 MHz). However, in order to achieve the clock speed the caches were reduced to 8 KB each and they took three cycles to access. The high operating frequencies were achieved through the technique of deep pipelining (called super-pipelining at the time). With the introduction of the R4000 a number of improved versions soon followed, including the R4400 (1993) which included 16 KB caches, largely bug-free 64-bit operation, and support for a larger external level 2 cache.

MIPS, now a division of SGI called MTI, designed the lower-cost R4200, and later the even lower cost R4300, which was the R4200 with a 32-bit external bus. The Nintendo 64 used a NEC VR4300 CPU that was based upon the low-cost MIPS R4300i.

Quantum Effect Devices (QED), a separate company started by former MIPS employees, designed the R4600 "Orion", the R4700 "Orion", the R4650 and the R5000. Where the R4000 had pushed clock frequency and sacrificed cache capacity, the QED designs emphasized large caches which could be accessed in just two cycles and efficient use of silicon area. The R4600 and R4700 were used in low-cost versions of the SGI Indy workstation as well as the first MIPS based Cisco routers, such as the 36x0 and 7x00-series routers. The R4650 was used in the original WebTV set-top boxes (now Microsoft TV). The R5000 FPU had more flexible single precision floating-point scheduling than the R4000, and as a result, R5000-based SGI Indys had much better graphics performance than similarly clocked R4400 Indys with the same graphics hardware. SGI gave the old graphics board a new name when it was combined with R5000 in order to emphasize the improvement. QED later designed the RM7000 and RM9000 family of devices for embedded markets like networking and laser printers. QED was acquired by the semiconductor manufacturer PMC-Sierra in August 2000, the latter company continuing to invest in the MIPS architecture. The RM7000 included an on-board 256 kB level 2 cache and a controller for optional level three cache. The RM9xx0 were a family of SOC devices which included northbridge peripherals such as memory controller, PCI controller, gigabit ethernet controller and fast IO such as a hypertransport port.

The R8000 (1994) was the first superscalar MIPS design, able to execute two integer or floating point and two memory instructions per cycle. The design was spread over six chips: an integer unit (with 16 KB instruction and 16 KB data caches), a floating-point unit, three full-custom secondary cache tag RAMs (two for secondary cache accesses, one for bus snooping), and a cache controller ASIC. The design had two fully pipelined double precision multiply-add units, which could stream data from the 4 MB off-chip secondary cache. The R8000 powered SGI's POWER Challenge servers in the mid 1990s and later became available in the POWER Indigo2 workstation. Although its FPU performance fit scientific users quite well, its limited integer performance and high cost dampened appeal for most users, and the R8000 was in the marketplace for only a year and remains fairly rare.

In 1995, the R10000 was released. This processor was a single-chip design, ran at a faster clock speed than the R8000, and had larger 32 KB primary instruction and data caches. It was also superscalar, but its major innovation was out-of-order execution. Even with a single memory pipeline and simpler FPU, the vastly improved integer performance, lower price, and higher density made the R10000 preferable for most customers.

Recent designs have all been based upon R10000 core. The R12000 used a 0.25 micrometre process to shrink the chip and achieve higher clock rates. The revised R14000 allowed higher clock rates with additional support for DDR SRAM in the off-chip cache, and a faster system bus clocked to 200 MHz for better throughput. Later iterations are named the R16000 and the R16000A and feature increased clock speed, additional L1 cache, and smaller die manufacturing compared with before.

Other members of the MIPS family include the R6000, an ECL implementation of the MIPS architecture which was produced by Bipolar Integrated Technology. The R6000 microprocessor introduced the MIPS II instruction set. Its TLB and cache architecture are different from all other members of the MIPS family. The R6000 did not deliver the promised performance benefits, and although it saw some use in Control Data machines, it quickly disappeared from the mainstream market.

Note: These specifications are for common processor models. Variations exist, especially in Level 2 cache.

Note: The R8000 has a unique cache hierarchy named 'Data Streaming Cache' where there is 16 KB of L1 data cache for the integer chip with an external 4 MB L2 cache that served as the secondary unified cache for the integer chip but as the L1 data cache for the floating point chip.

Instructions are divided into three types: R, I and J. Every instruction starts with a 6-bit opcode. In addition to the opcode, R-type instructions specify three registers, a shift amount field, and a function field; I-type instructions specify two registers and a 16-bit immediate value; J-type instructions follow the opcode with a 26-bit jump target.

These are assembly language instructions that have direct hardware implementation, as opposed to pseudoinstructions which are translated into multiple real instructions before being assembled.

MIPS has 32 integer ("fast") registers. Data must be in registers to perform arithmetic. Register $0 always holds 0 and register $1 is normally reserved for the assembler (for handling pseudo instructions and large constants).

The encoding shows which bits correspond to which parts of the instruction. A hyphen (-) is used to indicate don't cares.

NOTE: In MIPS assembler code, the offset for branching instructions can be represented by a label elsewhere in the code.

NOTE: that there is no corresponding "load lower immediate" instruction; this can be done by using addi (add immediate, see below) or ori (or immediate) with the register $0 (whose value is always zero). For example, both addi $1, $0, 100 and ori $1, $0, 100 load the decimal value 100 into register $1.

NOTE: Subtracting an immediate can be done with adding the negation of that value as the immediate.

MIPS has 32 floating-point registers. Two registers are paired for double precision numbers. Odd numbered registers cannot be used for arithemetic or branch, just for data transfer of the right "half" of double precision register pairs.

These instructions are accepted by the MIPS assembler, however they are not real instructions within the MIPS instruction set. Instead, the assembler translates them into sequences of real instructions.

These are the only hardware restrictions on the usage of the general purpose registers.

The various MIPS tool-chains implement specific calling conventions that further restrict how the registers are used. These calling conventions are totally maintained by the tool-chain software and are not required by the hardware.

Registers that are preserved across a call are registers that (by convention) will not be changed by a system call or procedure (function) call. For example, $s-registers must be saved to the stack by a procedure that needs to use them, and $sp and $fp are always incremented by constants, and decremented back after the procedure is done with them (and the memory they point to). By contrast, $ra is changed automatically by any normal function call (ones that use jal), and $t-registers must be saved by the program before any procedure call (if the program needs the values inside them after the call).

Open Virtual Platforms (OVP) includes the freely available simulator OVPsim, a library of models of processors, peripherals and platforms, and APIs which enable users to develop their own models. The models in the library are open source, written in C, and include the MIPS 4K, 24K and 34K cores. These models are created and maintained by Imperas and in partnership with MIPS Technologies have been tested and assigned the MIPS-Verified(tm) mark. The OVP site also includes models of ARM, Tensilica and OpenCores/openRisc processors. Sample MIPS-based platforms include both bare metal environments and platforms for booting unmodified Linux binary images. These platforms/emulators are available as source or binaries and are fast, free, and easy to use. OVPsim is developed and maintained by Imperas and is very fast (100s of million instructions per second), and built to handle multicore architectures. To download the MIPS OVPsim simulators/emulators visit .

More advanced free MIPS emulators are available from the GXemul (formerly known as the mips64emul project) and QEMU projects, which emulate not only the various MIPS III and higher microprocessors (from the R4000 through the R10000), but also entire computer systems which use the microprocessors. For example, GXemul can emulate both a DECstation with a MIPS R4400 CPU (and boot to Ultrix), and an SGI O2 with a MIPS R10000 CPU (although the ability to boot Irix is limited), among others, as well as the various framebuffers, SCSI controllers, and the like which comprise those systems.

Commercial simulators are available especially for the embedded use of MIPS processors, for example Virtutech Simics (MIPS 4Kc and 5Kc, PMC RM9000, QED RM7000), VaST Systems (R3000, R4000), and CoWare (the MIPS4KE, MIPS24K, MIPS25Kf and MIPS34K).

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The TecDAX stock index tracks the performance of the 30 largest German companies from the technology sector. The companies rank in terms of order book turnover and market capitalization rank below those included in the DAX.

TecDAX is based on prices generated in Xetra, an electronic trading system. Between 9am and 5.30pm CET the index is calculated on every trading day.

The following 30 companies make up the index as of the quarterly review effected on 23 March 2009 where Infineon Technologies replaced Manz Automation.

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SD Card Association

The SD Card Association develops and publishes technical standards for SD Card technology, and promotes the use of the technology. SD Cards are compact data storage devices used to store digital files, such as picture files recorded by digital cameras. The association was founded on 28 January 2000 by Matsushita Electric Industrial Co., Ltd. (Panasonic), SanDisk Corporation and Toshiba Corporation.

Board members of the association are Canon Inc., Eastman Kodak Company, Hewlett Packard, Industrial Technology Research Institute, Infineon Technologies AG, Kingston Technology Company, Matsushita Electric Industrial Co., Ltd., Motorola Inc., NEC Corporation, Nokia Corporation, Power Digital Card Co., Ltd., Samsung Electronics Co., Ltd., SanDisk Corporation, Sharp Corporation, Socket Mobile, Inc. and Toshiba Corporation.

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LSI Corporation

LSI Corporation is an electronics company based in Milpitas, California that designs ASICs, host bus adapters, RAID adapters, storage systems, and computer networking products.

LSI Corporation was founded in Milpitas, CA by Wilfred Corrigan as a semiconductor ASIC company after he left as CEO of Fairchild Semiconductor in 1979. The other three founders were Bill O'Meara (marketing and sales), Rob Walker (engineering) and Mitchell "Mick" Bohn (finance). The firm was founded in 1981, and initially funded with $6 million from noted venture capitalists including Sequoia Capital. A second round of financing for an additional $16M was completed in March 1982. The firm went public as LSI on Nasdaq on Friday May 13, 1983 - netting $153M, the largest tech IPO up to that date.

LSI built its own wafer fabrication, packaging and testing facilities in Milpitas as well as utilizing excess capacity at Toshiba for manufacturing - an early example of the fabless semiconductor manufacturing model. LSI Logic expanded world wide by establishing stand-alone affiliate companies in Japan, Europe and Canada. Nihon LSI Logic based in Tokyo, Japan was financed in April 1984 through a $20M private offering. LSI Logic Ltd based in Bracknell UK was financed in June 1984 by an additional $20M private placement and LSI Logic Canada based in Calgary, Alberta went public on the Toronto stock exchange. Each affiliate sought to develop independent manufacturing facilities through alliances, purchases or independent development. In 1985, the firm entered into a joint venture with Kawasaki Steel - Japan's third largest steel manufacturer - to build a $100M wafer fabrication plant in Tsukuba, Japan.

The firm developed the industry's first line of ASIC products which let customers create custom 'gate array' chips by use of leading-edge proprietary CAD tools (called LDS for 'Logic Design System'). The initial product lines were based on high-speed ECL (Emitter Coupled Logic) technology but soon switched over to high-speed CMOS (Complementary Metal Oxide Semiconductor) which offered much lower cost and lower power requirements to system designers. Over time, LSI Logic increased its product offerings and IP library through pioneering efforts in the areas of standard cells, structured arrays, DSPs and microprocessors (MIPS and SPARC) as it moved toward the complete design and development of "System on a Chip" solutions.

As the ASIC market matured, third party design tools became preeminent and with the very high cost of fab development, the foundry fab model gained momentum and LSI returned in 2005 to a fabless semiconductor business. During its ASIC years, LSI Logic invested in core technologies such as microprocessors, communication devices, and video compression devices such as MPEG. These core technologies have been used together with acquisitions to better place the firm as an intellectual property owner. In 1998 it bought Symbios Logic from Hyundai. In March 2001 LSI acquired C-Cube for $878M in stock. In 2006, the firm celebrated its 25th year of business.

On April 2, 2007, LSI completed its merger with Agere Systems, and rebranded the firm from LSI Logic Corporation to LSI Corporation. It is listed on the NYSE with the ticker symbol LSI.

In April, 2008 LSI formed the MSBG Alliance with Nortel Corporation, Accton Technology Corporation, Telrad Networks Ltd., Aricent Inc., Nakina Systems Inc., Dimark Technologies, Inc., VIA Technologies, Inc., Infineon Technologies AG, and Mediatrix Telecom.

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Source : Wikipedia