Memory Chips

3.3589001447312 (1382)
Posted by sonny 02/28/2009 @ 02:38

Tags : memory chips, semi conductors, technology

News headlines
Hynix Plans Chip Joint Venture in China - Wall Street Journal
The joint venture, now called Hynix-Numonyx Semiconductor Ltd., has both front-end and back-end chip plants. Chip makers such as Hynix have been suffering from a slump in demand for memory chips, leading them to cut their capital investments over the...
Rambus says FTC has dropped antitrust claims - The Associated Press
NEW YORK (AP) — Rambus Inc. said Thursday that the Federal Trade Commission has dropped its claim that the memory chip company violated antitrust laws in patenting technologies that were eventually incorporated into industry standards....
Micron move to graphics card chips - Atomic
By The Inquirer The memory business is no game, but that hasn't stopped DRAM maker Micron from diving headfirst into the graphics market with plans to supply memory chips for Nvidia and AMD gpus. According to CNET, Micron, the number three DRAM maker...
Samsung Elec: 2009 Very Tough Year For Chip Industry - Wall Street Journal
The company expects the industry's shipments of memory chips to continue to grow this year, although at a "much slower pace" compared to last year's, said Kwon during the Samsung Global Investors Conference hosted by Samsung Securities Monday....
A six pack of solid-state drives compared - The Tech Report, LLC
Thanks to smaller and denser memory chips, drives with capacities up to 256GB are easy to come by today. Such capacities may not match the multiple terabytes one can get with mechanical desktop drives, but they are more than adequate for most folks....
FTC dismisses case against Rambus - CIOL
LOS ALTOS, USA: Rambus Inc., one of the world's premier technology licensing companies specializing in high-speed memory architectures, announced that the Federal Trade Commission (FTC) has issued an order dismissing the remainder of its case against...
Chip Maker Elpida's Loss Doubles - Wall Street Journal
By JURO OSAWA TOKYO -- Elpida Memory Inc. said its net loss doubled in its fiscal fourth quarter as weak demand and low prices continue to dog the global semiconductor market. The loss at Japan's only maker of dynamic random access memory chips widened...
ZettaCore raises $21 million for nanotech-based chip memory - VentureBeat
But one company, ZettaCore, is soldiering on with a technique for using nanotech to create memory chips with ultra-tiny storage cells that can be packed densely. The company said Sunday that it raised $21 million in a third round of funding....
iPhone is a smashing success - WA today
The iPhone boasts a main processor and memory chips from Samsung Electronics, an audio-processing chip from Britain's Wolfson Microelectronics Plc and a Wi-fi wireless chip from Marvell Technology. Opening the iPhone was the easy part....
Memory Chips Signal Sector Getting Set For Recovery - Wall Street Journal
By EVAN RAMSTAD Memory chips appear to have hit the bottom of their business cycle, an important signal for the broader semiconductor industry, which has been suffering through its worst slump to date. Memory chips account for just 14% of the $260...

Flash memory

A flash memory cell.

Flash memory is a non-volatile computer memory that can be electrically erased and reprogrammed. It is a technology that is primarily used in memory cards and USB flash drives for general storage and transfer of data between computers and other digital products. It is a specific type of EEPROM (Electrically Erasable Programmable Read-Only Memory) that is erased and programmed in large blocks; in early flash the entire chip had to be erased at once. Flash memory costs far less than byte-programmable EEPROM and therefore has become the dominant technology wherever a significant amount of non-volatile, solid state storage is needed. Example applications include PDAs (personal digital assistants), laptop computers, digital audio players, digital cameras and mobile phones. It has also gained popularity in the game console market, where it is often used instead of EEPROMs or battery-powered SRAM for game save data.

Flash memory is non-volatile, which means that no power is needed to maintain the information stored in the chip. In addition, flash memory offers fast read access times (although not as fast as volatile DRAM memory used for main memory in PCs) and better kinetic shock resistance than hard disks. These characteristics explain the popularity of flash memory in portable devices. Another feature of flash memory is that when packaged in a "memory card," it is enormously durable, being able to withstand intense pressure, extremes of temperature, and even immersion in water.

Although technically a type of EEPROM, the term "EEPROM" is generally used to refer specifically to non-flash EEPROM which is erasable in small blocks, typically bytes. Because erase cycles are slow, the large block sizes used in flash memory erasing give it a significant speed advantage over old-style EEPROM when writing large amounts of data.

Flash memory (both NOR and NAND types) was invented by Dr. Fujio Masuoka while working for Toshiba circa 1980. According to Toshiba, the name "flash" was suggested by Dr. Masuoka's colleague, Mr. Shoji Ariizumi, because the erasure process of the memory contents reminded him of a flash of a camera. Dr. Masuoka presented the invention at the IEEE 1984 International Electron Devices Meeting (IEDM) held in San Francisco, California.

Intel saw the massive potential of the invention and introduced the first commercial NOR type flash chip in 1988. NOR-based flash has long erase and write times, but provides full address and data buses, allowing random access to any memory location. This makes it a suitable replacement for older ROM chips, which are used to store program code that rarely needs to be updated, such as a computer's BIOS or the firmware of set-top boxes. Its endurance is 10,000 to 1,000,000 erase cycles. NOR-based flash was the basis of early flash-based removable media; CompactFlash was originally based on it, though later cards moved to less expensive NAND flash.

Toshiba announced NAND flash at the 1987 International Electron Devices Meeting. It has faster erase and write times, and requires a smaller chip area per cell, thus allowing greater storage densities and lower costs per bit than NOR flash; it also has up to ten times the endurance of NOR flash. However, the I/O interface of NAND flash does not provide a random-access external address bus. Rather, data must be read on a block-wise basis, with typical block sizes of hundreds to thousands of bits. This made NAND flash unsuitable as a drop-in replacement for program ROM since most microprocessors and microcontrollers required byte-level random access. In this regard NAND flash is similar to other secondary storage devices such as hard disks and optical media, and is thus very suitable for use in mass-storage devices such as memory cards. The first NAND-based removable media format was SmartMedia, and many others have followed, including MultiMediaCard, Secure Digital, Memory Stick and xD-Picture Card. A new generation of memory card formats, including RS-MMC, miniSD and microSD, and Intelligent Stick, feature extremely small form factors. For example, the microSD card has an area of just over 1.5 cm², with a thickness of less than 1 mm; microSD capacities range from 64 MB to 16 GB, as of October 2008.

Despite the need for high programming and erasing voltages, virtually all flash chips today require only a single supply voltage, and produce the high voltages via on-chip charge pumps.

One limitation of flash memory is that although it can be read or programmed a byte or a word at a time in a random access fashion, it must be erased a "block" at a time. This generally sets all bits in the block to 1. Starting with a freshly erased block, any location within that block can be programmed. However, once a bit has been set to 0, only by erasing the entire block can it be changed back to 1. In other words, flash memory (specifically NOR flash) offers random-access read and programming operations, but cannot offer arbitrary random-access rewrite or erase operations. A location can, however, be rewritten as long as the new value's 0 bits are a superset of the over-written value's. For example, a nibble value may be erased to 1111, then written as 1110. Successive writes to that nibble can change it to 1010, then 0010, and finally 0000. In practice few algorithms take advantage of this successive write capability and in general the entire block is erased and rewritten at once.

Although data structures in flash memory cannot be updated in completely general ways, this allows members to be "removed" by marking them as invalid. This technique may need to be modified for multi-level devices, where one memory cell holds more than one bit.

Another limitation is that flash memory has a finite number of erase-write cycles. Most commercially available flash products are guaranteed to withstand around 100,000 write-erase-cycles, before the wear begins to deteriorate the integrity of the storage. The guaranteed cycle count may apply only to block zero (as is the case with TSOP NAND parts), or to all blocks (as in NOR). This effect is partially offset in some chip firmware or file system drivers by counting the writes and dynamically remapping blocks in order to spread write operations between sectors; this technique is called wear levelling. Another approach is to perform write verification and remapping to spare sectors in case of write failure, a technique called bad block management (BBM). For portable consumer devices, these wearout management techniques typically extend the life of the flash memory beyond the life of the device itself, and some data loss may be acceptable in these applications. For high reliability data storage, however, it is not advisable to use flash memory that would have to go through a large number of programming cycles. This limitation is meaningless for 'read-only' applications such as thin clients and routers, which are only programmed once or at most a few times during their lifetime.

The low-level interface to flash memory chips differs from those of other memory types such as DRAM, ROM, and EEPROM, which support bit-alterability (both zero to one and one to zero) and random-access via externally accessible address buses.

While NOR memory provides an external address bus for read and program operations (and thus supports random-access); unlocking and erasing NOR memory must proceed on a block-by-block basis. With NAND flash memory, read and programming operations must be performed page-at-a-time while unlocking and erasing must happen in block-wise fashion.

Reading from NOR flash is similar to reading from random-access memory, provided the address and data bus are mapped correctly. Because of this, most microprocessors can use NOR flash memory as execute in place (XIP) memory, meaning that programs stored in NOR flash can be executed directly without the need to first copy the program into RAM. NOR flash may be programmed in a random-access manner similar to reading. Programming changes bits from a logical one to a zero. Bits that are already zero are left unchanged. Erasure must happen a block at a time, and resets all the bits in the erased block back to one. Typical block sizes are 64, 128, or 256 KB.

Bad block management is a relatively new feature in NOR chips. In older NOR devices not supporting bad block management, the software or device driver controlling the memory chip must correct for blocks that wear out, or the device will cease to work reliably.

The specific commands used to lock, unlock, program, or erase NOR memories differ for each manufacturer. To avoid needing unique driver software for every device made, a special set of CFI commands allow the device to identify itself and its critical operating parameters.

Apart from being used as random-access ROM, NOR memories can also be used as storage devices by taking advantage of random-access programming. Some devices offer read-while-write functionality so that code continues to execute even while a program or erase operation is occurring in the background. For sequential data writes, NOR flash chips typically have slow write speeds compared with NAND flash.

NAND flash architecture was introduced by Toshiba in 1989. These memories are accessed much like block devices such as hard disks or memory cards. Each block consists of a number of pages. The pages are typically 512 or 2,048 or 4,096 bytes in size. Associated with each page are a few bytes (typically 12–16 bytes) that should be used for storage of an error detection and correction checksum.

While reading and programming is performed on a page basis, erasure can only be performed on a block basis. Another limitation of NAND flash is data in a block can only be written sequentially. Number of Operations (NOPs) is the number of times the sectors can be programmed. So far this number for MLC flash is always one whereas for SLC flash it is four.

NAND devices also require bad block management by the device driver software, or by a separate controller chip. SD cards, for example, include controller circuitry to perform bad block management and wear leveling. When a logical block is accessed by high-level software, it is mapped to a physical block by the device driver or controller. A number of blocks on the flash chip may be set aside for storing mapping tables to deal with bad blocks, or the system may simply check each block at power-up to create a bad block map in RAM. The overall memory capacity gradually shrinks as more blocks are marked as bad.

NAND relies on ECC to compensate for bits that may spontaneously fail during normal device operation. This ECC may correct as little as one bit error in each 2048 bits, or up to 22 bits in each 2048 bits. If ECC cannot correct the error during read, it may still detect the error. When doing erase or program operations, the device can detect blocks that fail to program or erase and mark them bad. The data is then written to a different, good block, and the bad block map is updated.

Most NAND devices are shipped from the factory with some bad blocks which are typically identified and marked according to a specified bad block marking strategy. By allowing some bad blocks, the manufacturers achieve far higher yields than would be possible if all blocks had to be verified good. This significantly reduces NAND flash costs and only slightly decreases the storage capacity of the parts.

When executing software from NAND memories, virtual memory strategies are often used: memory contents must first be paged or copied into memory-mapped RAM and executed there (leading to the common combination of NAND + RAM). A memory management unit (MMU) in the system is helpful, but this can also be accomplished with overlays. For this reason, some systems will use a combination of NOR and NAND memories, where a smaller NOR memory is used as software ROM and a larger NAND memory is partitioned with a file system for use as a nonvolatile data storage area.

NAND is best suited to systems requiring high capacity data storage. This type of flash architecture offers higher densities and larger capacities at lower cost with faster erase, sequential write, and sequential read speeds, sacrificing the random-access and execute in place advantage of the NOR architecture.

The ONFI group is supported by major NAND Flash manufacturers, including Hynix, Intel, Micron Technology, and Numonyx, as well as by major manufacturers of devices incorporating NAND flash chips.

A group of vendors, including Intel, Dell, and Microsoft formed a Non-Volatile Memory Host Controller Interface (NVMHCI) Working Group. The goal of the group is to provide standard software and hardware programming interfaces for nonvolatile memory subsystems, including the "flash cache" device connected to the PCI Express bus.

It is important to understand that these two are linked by the design choices made in the development of NAND flash. An important goal of NAND flash development was to reduce the chip area required to implement a given capacity of flash memory, and thereby to reduce cost per bit and increase maximum chip capacity so that flash memory could compete with magnetic storage devices like hard disks.

NOR and NAND flash get their names from the structure of the interconnections between memory cells. In NOR flash, cells are connected in parallel to the bit lines, allowing cells to be read and programmed individually. The parallel connection of cells resembles the parallel connection of transistors in a CMOS NOR gate. In NAND flash, cells are connected in series, resembling a NAND gate, and preventing cells from being read and programmed individually: the cells connected in series must be read in series.

When NOR flash was developed, it was envisioned as a more economical and conveniently rewritable ROM than contemporary EPROM, EAROM, and EEPROM memories. Thus random-access reading circuitry was necessary. However, it was expected that NOR flash ROM would be read much more often than written, so the write circuitry included was fairly slow and could only erase in a block-wise fashion; random-access write circuitry would add to the complexity and cost unnecessarily.

Because of the series connection and removal of wordline contacts, a large grid of NAND flash memory cells will occupy perhaps only 60% of the area of equivalent NOR cells (assuming the same CMOS process resolution, e.g. 130 nm, 90 nm, 65 nm). NAND flash's designers realized that the area of a NAND chip, and thus the cost, could be further reduced by removing the external address and data bus circuitry. Instead, external devices could communicate with NAND flash via sequential-accessed command and data registers, which would internally retrieve and output the necessary data. This design choice made random-access of NAND flash memory impossible, but the goal of NAND flash was to replace hard disks, not to replace ROMs.

The write endurance of SLC Floating Gate NOR flash is typically equal or greater than that of NAND flash, while MLC NOR & NAND Flash have similar Endurance capabilities. Example Endurance cycle ratings listed in datasheets for NAND and NOR Flash are provided.

Because of the particular characteristics of flash memory, it is best used with either a controller to perform wear-levelling and error correction or specifically designed flash file systems, which spread writes over the media and deal with the long erase times of NOR flash blocks. The basic concept behind flash file systems is: When the flash store is to be updated, the file system will write a new copy of the changed data over to a fresh block, remap the file pointers, then erase the old block later when it has time.

In practice, flash file systems are only used for "Memory Technology Devices" ("MTD"), which are embedded flash memories that do not have a controller. Removable flash memory cards and USB flash drives have built-in controllers to perform wear-levelling and error correction so use of a specific flash file system does not add any benefit. These removable flash memory devices use the FAT file system to allow universal compatibility with computers, cameras, PDAs and other portable devices with memory card slots or ports.

Multiple chips are often arrayed to achieve higher capacities for use in consumer electronic devices such as multimedia players or GPS. The capacity of flash chips generally follows Moore's Law because they are manufactured with many of the same integrated circuits techniques and equipment.

Consumer flash drives typically have sizes measured in powers of two (e.g. 512 MB, 8 GB). This includes SSDs as hard drive replacements, even though traditional hard drives tend to use decimal units. Thus, a 64 GB SSD is actually 64 × 10243 bytes. In reality, most users will have slightly less capacity than this available, due to the space taken by filesystem metadata.

In 2005, Toshiba and SanDisk developed a NAND flash chip capable of storing 1 GB of data using Multi-level Cell (MLC) technology, capable of storing 2 bits of data per cell. In September 2005, Samsung Electronics announced that it had developed the world’s first 2 GB chip.

In March 2006, Samsung announced flash hard drives with a capacity of 4 GB, essentially the same order of magnitude as smaller laptop hard drives, and in September 2006, Samsung announced an 8 GB chip produced using a 40 nanometer manufacturing process.

In January 2008 Sandisk announced availability of their 16 GB MicroSDHC and 32 GB SDHC Plus cards.

But there are still flash-chips manufactured with low capacities like 1 MB, e.g., for BIOS-ROMs.

Commonly advertised is the maximum read speed, NAND flash memory cards are much faster at reading than writing. As a chip gets worn out, its erase/program operations slow down considerably, requiring more retries and bad block remapping. Transferring multiple small files, smaller than the chip specific block size, could lead to much lower rate. Access latency has an influence on performance but is less of an issue than with their hard drive counterpart.

The speed is sometimes quoted in MB/s (megabytes per second), or as a multiple of that of a legacy single speed CD-ROM, such as 60x, 100x or 150x. Here 1x is equivalent to 150 kilobytes per second. For example, a 100x memory card gives 150 KB x 100 = 15000 KB/s = 14.65 MB/s.

Serial flash is a small, low-power flash memory that uses a serial interface, typically SPI, for sequential data access. When incorporated into an embedded system, serial flash requires fewer wires on the PCB than parallel flash memories, since it transmits and receives data one bit at a time. This may permit a reduction in board space, power consumption, and total system cost.

With the increasing speed of modern CPUs, parallel flash devices are often much slower than the memory bus of the computer they are connected to. Conversely, modern SRAM offers access times below 10 ns, while DDR2 SDRAM offers access times below 20 ns. Because of this, it is often desirable to shadow code stored in flash into RAM; that is, the code is copied from flash into RAM before execution, so that the CPU may access it at full speed. Device firmware may be stored in a serial flash device, and then copied into SDRAM or SRAM when the device is powered-up. Using an external serial flash device rather than on-chip flash removes the need for significant process compromise (a process that is good for high speed logic is generally not good for flash and vice-versa). Once it is decided to read the firmware in as one big block it is common to add compression to allow a smaller flash chip to be used. Typical applications for serial flash include storing firmware for hard drives, Ethernet controllers, DSL modems, wireless network devices, etc.

An obvious extension of flash memory would be as a replacement for hard disks. Flash memory does not have the mechanical limitations and latencies of hard drives, so the idea of a solid-state drive, or SSD, is attractive when considering speed, noise, power consumption, and reliability.

There remain some aspects of flash-based SSDs that make the idea unattractive. Most important, the cost per gigabyte of flash memory remains significantly higher than that of platter-based hard drives. Although this ratio is decreasing rapidly for flash memory, it is not yet clear that flash memory will catch up to the capacities and affordability offered by platter-based storage. Still, research and development is sufficiently vigorous that it is not clear that it will not happen, either.

There is also some concern that the finite number of erase/write cycles of flash memory would render flash memory unable to support an operating system. This seems to be a decreasing issue as warranties on flash-based SSDs are approaching those of current hard drives.

As of May 24, 2006, South Korean consumer-electronics manufacturer Samsung Electronics had released the first flash-memory based PCs, the Q1-SSD and Q30-SSD, both of which have 32 GB SSDs. Dell Computer introduced the Latitude D430 laptop with 32 GB flash-memory storage in July 2007 -- at a price significantly above a hard-drive equipped version.

At the Las Vegas CES 2007 Summit Taiwanese memory company A-DATA showcased SSD hard disk drives based on Flash technology in capacities of 32 GB, 64 GB and 128 GB. Sandisk announced an OEM 32 GB 1.8" SSD drive at CES 2007. The XO-1, developed by the One Laptop Per Child (OLPC) association, uses flash memory rather than a hard drive. As of June 2007, a South Korean company called Mtron claims the fastest SSD with sequential read/write speeds of 100 MB/80 MB per second.

Rather than entirely replacing the hard drive, hybrid techniques such as hybrid drive and ReadyBoost attempt to combine the advantages of both technologies, using flash as a high-speed cache for files on the disk that are often referenced, but rarely modified, such as application and operating system executable files. Also, Addonics has a PCI adapter for 4 CF cards, creating a RAID-able array of solid-state storage that is much cheaper than the hardwired-chips PCI card kind.

The ASUS Eee PC uses a flash-based SSD of 2 GB to 20 GB, depending on model. The Apple Inc. Macbook Air has the option to upgrade the standard hard drive to a 128 GB Solid State hard drive. The Lenovo ThinkPad X300 also features a built-in 64 GB Solid State Drive.

Sharkoon has devoloped a device that uses six SDHC cards in RAID-0 as an SSD alternative; users may use more affordable High-Speed 8GB SDHC cards to get similar or better results than can be obtained from traditional SSDs at a lower cost.

One source states that, in 2008, the flash memory industry includes about US$9.1 billion in production and sales. Apple Inc. is the third largest purchaser of flash memory, consuming about 13% of production by itself. Other sources put the flash memory market at a size of more than US$20 billion in 2006, accounting for more than eight percent of the overall semiconductor market and more than 34 percent of the total semiconductor memory market.

Due to its relatively simple structure and high demand for higher capacity, NAND Flash memory is the most aggressively scaled technology among electronic devices. The heavy competition among the top few manufacturers only adds to the aggression. Current projections show the technology to reach approximately 20 nm by around 2010. While the expected shrink timeline is a factor of two every three years per original version of Moore's law, this has recently been accelerated in the case of NAND flash to a factor of two every two years.

As the feature size of Flash memory cells reach the minimum limit (currently estimated ~20 nm), further Flash density increases will be driven by greater levels of MLC, possibly 3-D stacking of transistors, and process improvements. Even with these advances, it may be impossible to economically scale Flash to smaller and smaller dimensions. Many promising new technologies (such as FeRAM, MRAM, PMC, PCM, and others) are under investigation and development as possible more scalable replacements for Flash.

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Dynamic random access memory

Common DRAM packages.  From top to bottom: DIP, SIPP, SIMM 30 pin, SIMM 72 pin, DIMM (168-pin), DDR DIMM (184-pin).

Dynamic random access memory (DRAM) is a type of random access memory that stores each bit of data in a separate capacitor within an integrated circuit. Since real capacitors leak charge, the information eventually fades unless the capacitor charge is refreshed periodically. Because of this refresh requirement, it is a dynamic memory as opposed to SRAM and other static memory.

The advantage of DRAM is its structural simplicity: only one transistor and a capacitor are required per bit, compared to six transistors in SRAM. This allows DRAM to reach very high density. Unlike Flash memory, it is volatile memory (cf. non-volatile memory), since it loses its data when the power supply is removed.

In 1964, Arnold Farber and Eugene Schlig working for IBM created a memory cell that was hard wired; using a transistor gate and tunnel diode latch, they later replaced the latch with two transistors and two resistors, which became known as the Farber-Schlig cell. In 1965, Benjamin Agusta and his team working for IBM managed to create a 16-bit silicon chip memory cell based on the Farber-Schlig cell which consisted of 80 transistors, 64 resistors and 4 diodes. In 1966 DRAM was invented by Dr. Robert Dennard at the IBM Thomas J. Watson Research Center and he was awarded U.S. patent number 3,387,286 in 1968. Capacitors had been used for earlier memory schemes such as the drum of the Atanasoff–Berry Computer, the Williams tube and the Selectron tube.

The Toshiba "Toscal" BC-1411 electronic calculator, which went into production in November 1965, uses a form of dynamic RAM built from discrete components.

In 1969 Honeywell asked Intel to make a DRAM using a 3-transistor cell that they had developed. This became the Intel 1102 (1024x1) in early 1970. However the 1102 had many problems, prompting Intel to begin work on their own improved design (in secrecy to avoid conflict with Honeywell). This became the first commercially-available DRAM memory, the Intel 1103 (1024x1) in October 1970 (despite initial problems with low yield until the 5th revision of the masks).

DRAM is usually arranged in a square array of one capacitor and transistor per cell. The illustrations to the right show a simple example with only 4 by 4 cells (modern DRAM can be thousands of cells in length/width).

The long lines connecting each row are known as word lines. Each column is actually composed of two bit lines, each one connected to every other storage cell in the column. (The illustration to the right does not include this important detail.) They are generally known as the + and − bit lines. A sense amplifier is essentially a pair of cross-connected inverters between the bit lines. That is, the first inverter is connected from the + bit line to the − bit line, and the second is connected from the − bit line to the + bit line. This is an example of positive feedback, and the arrangement is only stable with one bit line high and one bit line low.

To write to memory, the row is opened and a given column's sense amplifier is temporarily forced to the desired state, so it drives the bit line which charges the capacitor to the desired value. Due to the positive feedback, the amplifier will then hold it stable even after the forcing is removed. During a write to a particular cell, the entire row is read out, one value changed, and then the entire row is written back in, as illustrated in the figure to the right.

Thus, the generally quoted number is the /RAS access time. This is the time to read a random bit from a precharged DRAM array. The time to read additional bits from an open page is much less.

When such a RAM is accessed by clocked logic, the times are generally rounded up to the nearest clock cycle. For example, when accessed by a 100 MHz state machine (i.e. a 10 ns clock), the 50 ns DRAM can perform the first read in 5 clock cycles, and additional reads within the same page every 2 clock cycles. This was generally described as "5-2-2-2" timing, as bursts of 4 reads within a page were common.

When describing synchronous memory, timing is also described by clock cycle counts separated by hyphens, but the numbers have very different meanings! These numbers represent tCAS-tRCD-tRP-tRAS in multiples of the DRAM clock cycle time. Note that this is half of the data transfer rate when double data rate signaling is used. JEDEC standard PC3200 timing is 3-4-4-8 with a 200 MHz clock, while premium-priced high performance PC3200 DDR DRAM DIMM might be operated at 2-2-2-5 timing.

It is worth noting that the improvement over 11 years is not that large. Minimum random access time has improved from 50 ns to tRCD + tCL = 23.5 ns, and even the premium 20 ns variety is only 2.5× better. However, the DDR3 memory does achieve 32 times higher bandwidth; due to internal pipelining and wide data paths, it can output two words every 1.25 ns (1600 Mword/s), while the EDO DRAM can output one word per tPC = 20 ns (50 Mword/s).

Electrical or magnetic interference inside a computer system can cause a single bit of DRAM to spontaneously flip to the opposite state. It was initially thought that this was mainly due to alpha particles emitted by contaminants in chip packaging material, but research has shown that the majority of one-off ("soft") errors in DRAM chips occur as a result of background radiation, chiefly neutrons from cosmic ray secondaries which may change the contents of one or more memory cells, or interfere with the circuitry used to read/write them. There is some concern that as DRAM density increases further, and thus the components on DRAM chips get smaller, whilst at the same time operating voltages continue to fall, DRAM chips will be affected by such radiation more frequently - since lower energy particles will be able to change a memory cell's state. On the other hand, smaller cells make smaller targets, and moves to technologies such as SOI may make individual cells less susceptible and so counteract, or even reverse this trend.

This problem can be mitigated by using DRAM modules that include extra memory bits and memory controllers that exploit these bits. These extra bits are used to record parity or to use an error-correcting code (ECC). Parity allows the detection of a single-bit error (actually, any odd number of wrong bits). The most common error correcting code, Hamming code, allows a single-bit error to be corrected and (in the usual configuration, with an extra parity bit) double-bit errors to be detected.

Error detection and correction in computer systems seems to go in and out of fashion. Seymour Cray famously said "parity is for farmers" when asked why he left this out of the CDC 6600. He included parity in the CDC 7600, and reputedly said "I learned that a lot of farmers buy computers." The original IBM PC and all PCs until the early 1990s used parity checking. Later ones mostly did not. Wider memory buses make parity and especially ECC more affordable. Many current microprocessor memory controllers, including almost all AMD 64-bit offerings, support ECC, but many motherboards and in particular those using low-end chipsets do not.

Error detection and correction depends on an expectation of the kinds of errors that occur. Implicitly, we have assumed that the failure of each bit in a word of memory is independent and hence that two simultaneous errors are improbable. This used to be the case when memory chips were one bit wide (typical in the first half of the 1980s). Now many bits are in the same chip. This weakness does not seem to be widely addressed; one exception is Chipkill.

Testsgive widely varying error rates, but about 10-12upset/bit-hr is typical, roughly one bit error, per month, per gigabyte of memory.

In most computers used for serious scientific or financial computing and as servers, ECC is the rule rather than the exception, as can be seen by examining manufacturers' specifications.

For economic reasons, the large (main) memories found in personal computers, workstations, and non-handheld game-consoles (such as Playstation and Xbox) normally consists of dynamic RAM (DRAM). Other parts of the computer, such as cache memories and data buffers in hard disks, normally use static RAM (SRAM).

This interface provides direct control of internal timing. When /RAS is driven low, a /CAS cycle must not be attempted until the sense amplifiers have sensed the memory state, and /RAS must not be returned high until the storage cells have been refreshed. When /RAS is driven high, it must be held high long enough for precharging to complete.

VRAM is a dual-ported variant of DRAM which was once commonly used to store the frame-buffer in some graphics adaptors.

It was invented by F. Dill and R. Matick at IBM Research in 1980, with a patent issued in 1985 (US Patent 4,541,075). The first commercial use of VRAM was in the high resolution graphics adapter introduced in 1986 by IBM with the PC/RT system.

VRAM has two sets of data output pins, and thus two ports that can be used simultaneously. The first port, the DRAM port, is accessed by the host computer in a manner very similar to traditional DRAM. The second port, the video port, is typically read-only and is dedicated to providing a high bandwidth data channel for the graphics chipset.

Typical DRAM arrays normally access a full row of bits (i.e. a word line) at up to 1024 bits at one time, but only use one or a few of these for actual data, the remainder being discarded. Since DRAM cells are destructively read, each bit accessed must be sensed, and re-written. Thus, typically, 1024 sense amplifiers are typically used. VRAM operates by not discarding the excess bits which must be accessed, but making full use of them in a simple way. If each horizontal scan line of a display is mapped to a full word, then upon reading one word and latching all 1024 bits into a separate row buffer, these bits can subsequently be serially streamed to the display circuitry. This will leave access to the DRAM array free to be accessed (read or write) for many cycles, until the row buffer is almost depleted. A complete DRAM read cycle is only required to fill the row buffer, leaving most DRAM cycles available for normal accesses.

Such operation is described in the paper "All points addressable raster display memory" by R. Matick, D. Ling, S. Gupta, and F. Dill, IBM Journal of R&D, Vol 28, No. 4, July 1984, pp379-393. To use the video port, the controller first uses the DRAM port to select the row of the memory array that is to be displayed. The VRAM then copies that entire row to an internal row-buffer which is a shift-register. The controller can then continue to use the DRAM port for drawing objects on the display. Meanwhile, the controller feeds a clock called the shift clock (SCLK) to the VRAM's video port. Each SCLK pulse causes the VRAM to deliver the next datum, in strict address order, from the shift-register to the video port. For simplicity, the graphics adapter is usually designed so that the contents of a row, and therefore the contents of the shift-register, corresponds to a complete horizontal line on the display.

In the late 1990s, standard DRAM technologies (e.g. SDRAM) became cheap, dense, and high performance enough to completely displace VRAM, even though it was only single-ported and some memory bits were wasted.

Fast page mode DRAM is also called FPM DRAM, Page mode DRAM, Fast page mode memory, or Page mode memory.

In page mode, a row of the DRAM can be kept "open" by holding /RAS low while performing multiple reads or writes with separate pulses of /CAS. so that successive reads or writes within the row do not suffer the delay of precharge and accessing the row. This increases the performance of the system when reading or writing bursts of data.

Static column is a variant of page mode in which the column address does not need to be strobed in, but rather, the address inputs may be changed with /CAS held low, and the data output will be updated accordingly a few nanoseconds later.

Nibble mode is another variant in which four sequential locations within the row can be accessed with four consecutive pulses of /CAS. The difference from normal page mode is that the address inputs are not used for the second through fourth /CAS edges; they are generated internally starting with the address supplied for the first /CAS edge.

Classic asynchronous DRAM is refreshed by opening each row in turn. This can be done by supplying a row address and pulsing /RAS low; it is not necessary to perform any /CAS cycles. An external counter is needed to iterate over the row addresses in turn.

For convenience, the counter was quickly incorporated into RAM chips themselves. If the /CAS line is driven low before /RAS (normally an illegal operation), then the DRAM ignores the address inputs and uses an internal counter to select the row to open. This is known as /CAS-before-/RAS (CBR) refresh.

This became the standard form of refresh for asynchronous DRAM, and is the only form generally used with SDRAM.

EDO DRAM is similar to Fast Page Mode DRAM with the additional feature that a new access cycle can be started while keeping the data output of the previous cycle active. This allows a certain amount of overlap in operation (pipelining), allowing somewhat improved performance. It was 5% faster than Fast Page Mode DRAM, which it began to replace in 1993.

To be precise, EDO DRAM begins data output on the falling edge of /CAS, but does not stop the output when /CAS rises again. It holds the output valid (thus extending the data output time) until either /RAS is deasserted, or a new /CAS falling edge selects a different column address.

Single-cycle EDO has the ability to carry out a complete memory transaction in one clock cycle. Otherwise, each sequential RAM access within the same page takes two clock cycles instead of three, once the page has been selected. EDO's performance and capabilities allowed it to somewhat replace the then-slow L2 caches of PCs. It created an opportunity to reduce the immense performance loss associated with a lack of L2 cache, while making systems cheaper to build. This was also good for notebooks due to difficulties with their limited form factor, and battery life limitations. An EDO system with L2 cache was tangibly faster than the older FPM/L2 combination.

Single-cycle EDO DRAM became very popular on video cards towards the end of the 1990s. It was very low cost, yet nearly as efficient for performance as the far more costly VRAM.

EDO was sometimes referred to as Hyper Page Mode.

An evolution of the former, Burst EDO DRAM, could process four memory addresses in one burst, for a maximum of 5-1-1-1, saving an additional three clocks over optimally designed EDO memory. It was done by adding an address counter on the chip to keep track of the next address. BEDO also added a pipelined stage allowing page-access cycle to be divided into two components. During a memory-read operation, the first component accessed the data from the memory array to the output stage (second latch). The second component drove the data bus from this latch at the appropriate logic level. Since the data is already in the output buffer, quicker access time is achieved (up to 50% for large blocks of data) than with traditional EDO.

Although BEDO DRAM showed additional optimization over EDO, by the time it was available the market had made a significant investment towards synchronous DRAM, or SDRAM . Even though BEDO RAM was superior to SDRAM in some ways, the latter technology gained significant traction and quickly displaced BEDO.

BEDO slightly improved upon EDO, but was inferior to SDRAM, which was introduced at about the same time, and so never became popular.

Multibank RAM applies the interleaving technique for main memory to second level cache memory to provide a cheaper and faster alternative to SRAM. The chip splits its memory capacity into small blocks of 256 kB and allows operations to two different banks in a single clock cycle.

This memory was primarily used in graphic cards with Tseng Labs ET6x00 chipsets, and was made by MoSys. Boards based upon this chipset often used the unusual RAM size configuration of 2.25 MiB, owing to MDRAM's ability to be implemented in various sizes more easily. This size of 2.25 MiB allowed 24-bit color at a resolution of 1024×768, a very popular display setting in the card's time.

SGRAM is a specialized form of SDRAM for graphics adaptors. It adds functions such as bit masking (writing to a specified bit plane without affecting the others) and block write (filling a block of memory with a single colour). Unlike VRAM and WRAM, SGRAM is single-ported. However, it can open two memory pages at once, which simulates the dual-port nature of other video RAM technologies.

Single Data Rate (SDR) SDRAM is a synchronous form of DRAM.

Direct RAMBUS DRAM (DRDRAM).....

Double data rate (DDR) SDRAM was a later development of SDRAM, used in PC memory beginning in 2000. DDR2 SDRAM was originally seen as a minor enhancement (based upon the industry standard single-core CPU) on DDR SDRAM that mainly afforded higher clock rates and somewhat deeper pipelining. However, with the introduction and rapid acceptance of the multi-core CPU in 2006, it is generally expected in the industry that DDR2 will revolutionize the existing physical DDR-SDRAM standard. Further, with the development and introduction of DDR3 SDRAM in 2007, it is anticipated DDR3 will rapidly replace the more limited DDR and newer DDR2.

Some DRAM components have a "self-refresh mode". While this involves much of the same logic that is needed for pseudo-static operation, this mode is often equivalent to a standby mode. It is provided primarily to allow a system to suspend operation of its DRAM controller to save power without losing data stored in DRAM, not to allow operation without a separate DRAM controller as is the case with PSRAM.

An embedded variant of pseudostatic RAM is sold by MoSys under the name 1T-SRAM. It is technically DRAM, but behaves much like SRAM. It is used in Nintendo Gamecube and Wii consoles.

1T DRAM is commercialized under the name Z-RAM.

Note that classic one-transistor/one-capacitor (1T/1C) DRAM cell is also sometimes referred to as "1T DRAM".

Reduced Latency DRAM is a high performance double data rate (DDR) SDRAM that combines fast, random access with high bandwidth. RLDRAM is mainly designed for networking and caching applications.

Although dynamic memory is only guaranteed to retain its contents when supplied with power and refreshed every 64 ms, the memory cell capacitors will often retain their values for significantly longer, particularly at low temperatures.

Under some conditions, most of the data in DRAM can be recovered even if the DRAM has not been refreshed for several minutes.

This property can be used to recover "secure" data kept in memory by quickly rebooting the computer and dumping the contents of the RAM or by cooling the chips and transferring them to a different computer. Such an attack was demonstrated to circumvent popular disk encryption systems, like the open source TrueCrypt, Microsoft's BitLocker Drive Encryption, as well as Apple's FileVault.

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ROM image

A ROM dumping device for the Game Boy Advance.

A ROM image, or simply ROM, is a computer file which contains a copy of the data from a read-only memory chip, often from a video game cartridge, a computer's firmware, or from an arcade game's main board. The term is frequently used in the context of emulation, whereby older games or computer firmware are copied to ROM files on modern computers and can, using a piece of software known as an emulator, be run on the newer computer.

ROM images are also used when developing for embedded computers. Software which is being developed for embedded computers is often written to ROM files for testing on a standard computer before it is written to a ROM chip for use in the embedded system. At present, this article deals mainly with the use of ROM in relation to emulation.

ROM chips, while still in use, have been replaced in many instances by optical media such as CD-ROMs and DVD-ROMs, magnetic media such as hard disks and magnetic tapes and, more recently, Flash Memory chips. However, the term ROM is commonly also used to cover many of these newer media so, for instance, a computer game copied from a magnetic tape may also be incorrectly referred to as a ROM. The correct names for tape and disk 'roms' are Tape image and Disk image respectively. Images copied from optical media are also called ISO images, after one of the standard file systems for optical media, ISO 9660. Many ROMs used by emulators, and particularly console emulators, are not true images of the ROM chips in the cartridge. They are often modified to allow easier functionality in emulators through methods such as combining the images from multiple ROM chips.

ROMs can be copied from the read-only memory chips found in cartridge-based games and many arcade machines using a dedicated device in a process known as dumping. For most common home video game systems, these devices are widely available. Dumping ROMs from arcade machines, which in fact are highly customized PCBs, often requires individual setups for each machine along with a large amount of expertise.

Creating images from other media is often considerably easier and can often be performed with off-the-shelf hardware. For example, the creation of tape images from games stored on magnetic tapes (from, for example, the Sinclair ZX80 computer) generally involves simply playing the magnetic tape using a standard audio tape player connected to the line-in of a PC sound card. This is then recorded to an audio file and transformed into a tape image file using another program. Likewise, many CD and DVD games may be copied using a standard PC CD/DVD drive.

The lifespan of digital media is rarely great. While black-and-white photographs may survive for a century or more, many digital media can become unreadable after only 10 years. This is beginning to become a problem as early computer systems may be presently fifty or sixty years old while early home video consoles may be almost thirty years old. Due to this aging, there is a significant worry that many early computer and video games may not survive without being transferred to new media. So, those with an interest in preservation are actively seeking older arcade and video games and attempting to dump them to ROMs. When stored on standardized media such as CD-ROMs and DVD-ROMs, they can be copied to future media with significantly reduced effort.

The trend towards mass digital distribution of ROMs images, while potentially damaging to copyright holders, may also have a positive effect on preservation. While over time many original copies of older games may deteriorate, be broken or thrown away, a copy in ROM or Image form may be distributed throughout the world, allowing games which would otherwise have been lost a greater chance of survival.

While ROM images are often used as a means of preserving the history of computer games, they are also often used to facilitate the unauthorized copying and redistribution of modern games. Seeing this as potentially reducing sales of their products, many game companies have incorporated features into newer games which are designed to prevent copying, while still allowing the original game to be played. For instance, the Nintendo GameCube used non-standard 8 cm DVD-like optical media which for a long time prevented games from being copied to PCs. It was not until a security hole was found in Phantasy Star Online Episode I & II that GameCube games could be successfully copied to a PC, using the Gamecube itself to read the discs.

SNK also employed a protection on their Neo Geo games starting with The King of Fighters in 1999 which used an encryption algorithm on the graphics ROMs which prevented them from being played in an emulator. Many thought that this would mark the end of NeoGeo emulation. However, as early as 2000, crackers found a way to decrypt and dump the ROMs successfully, making them playable once again in any NeoGeo emulator.

Another company which used to protect their arcade games was Capcom which is known for its Capcom Play System II arcade board. This contained a heavy copy protection algorithm which was not broken until 7 years after the system's release in 1993. The original crack by the CPS2Shock Team was not a true emulation of the protection because it used XOR tables to trick the game into decrypting and play in an emulator. Their stated intent was to wait until CPS-2 games were no longer profitable to release the decryption method (three years after the last game release). The full decryption algorithm was cracked in 2007 by Nicola Salmoria, Andreas Naive and Charles MacDonald of the MAME development team.

Another copy protection technique used in cartridge-games was to have the game attempt to write to ROM. On an authentic cartridge this would fail or cause an exception, however, emulators would often allow the write to succeed. Pirate cartridges also often used writable chips instead of ROM. By reading the value back to see whether the write succeeded, the game could tell whether it was running from an authentic cartridge. Alternatively, the game may simply attempt to overwrite critical program instructions, which if successful renders it unplayable.

Some games, such as Game Boy games, also had other hardware such as memory bank controllers connected to the cartridge bus. The game would send data to this hardware by attempting to write it to specific areas of ROM; thus, if the ROM were writable, this process would corrupt data.

Capcom's latest arcade board is the CPS-3. This was resistant to emulation attempts until June 2007, when the encryption method was reverse-engineered by Andreas Naive. It is currently implemented by MAME and a variant of the CPS-2 emulator Nebula.

Like many other items such as stamps and coins, ROMs are also collected by many people. The motives for doing this vary from a desire to preserve the history of computer and video games to obsessive collectors. Those who desire to collect all ROMs have been derided by the MAME developers as PokéROMs, in a reference to the Pokémon catchphrase "gotta catch 'em all." PokéROM can also refer to "Pocket ROMs" as Pokémon refers to "Pocket Monsters"; since the advent of the GP2X, PSP, DS and other portable handheld gaming machines capable of emulation and even with some Cellphones, people can now have an entire library of old games in their "pocket".

Given the desire by many people to collect ROMs, there are many projects on the internet which dump ROMs, catalogue them or provide tools to verify the correctness and completeness of ROM collections. However, it is illegal to download copyrighted ROMs from the internet. Most old games are copyrighted.

Although the large size of games for recent consoles makes the distribution of more than one game at a time impractical, it is often the case for older consoles that many thousands of games can be distributed together as a collection. Larger games are often distributed one by one.

Once games have been made available in ROM format, it is possible for users to make modifications. This may take the form of altering graphics, changing game levels, tweaking difficulty factor, or even translation into a language for which a game was not originally made available. Hacks can often take humorous forms, as is the case with a hack of the NES version of Mario Bros., entitled Afro Mario Brothers, which features the famous brothers wearing Afro haircuts. The Metroid Redesign mod is a hack of Super Metroid that revamps the game and adds new objectives.

A large scene has developed to translate games into other languages. Many games receive a release in one part of the world, but not in another. For example, many computer role-playing games released in Japan go unreleased in the West. A group of fan translators will often translate the game themselves to meet obvious demand for titles. For example, the 1995 game Tales of Phantasia was only officially released in Japan; DeJap Translations translated the game's on-screen text into English in 2001. Further to this, a project called Vocals of Phantasia was begun to translate the actual speech from the game. An official English version was not released until March 2006, some five years after the text translation was released.

The Japanese N64 game 'Dōbutsu no Mori' (Animal Forest) has also been translated into English. The game was originally only released on N64 in Japan, but it was ported to GameCube and renamed Animal Crossing.

Hacks may range from simple tweaks such as graphic fixes and cheats, to full-blown redesigns of the game, in effect creating an entirely new game using the original as a base.

One of the oldest games that has an active ROM hacking scene to this day is Super Mario Bros.

ROMs themselves are not illegal per se. This section gives a general discussion of the legal status of ROMs as regards the various uses to which they may be put, though this should not be construed as legal advice.

In some countries, it is legal for an individual to personally make backup copies of a game they own. Individuals may make backup copies for various reasons, perhaps as insurance against losing the game or as redundancy in the event that the original game's medium becomes unreadable. See the section on ROMs and Preservation.

However, in the U.S. it has been illegal since 1983 for a user to create their own backups of video game ROMs onto other cartridges. This was decided in the court case of Atari v. JS&A. JS&A manufactured a "game backup" device that allowed users to dump their Atari ROMs onto a blank cartridge. JS&A argued that the archival rule allowed for this. The court disagreed, noting that ROM media was not subject to the same volatility as magnetic media (for which the law was created). Thus, not being so relatively vulnerable, ROMs were not applicable under section 17 USC 117(a)(2).

Some games companies, such as Nintendo, print warnings inside their game manuals that they do not allow users to make backup or archival copies. Whether or not these warnings in this specific form can be considered valid contracts is legally questionable. For an overview of relevant issues, see user agreement (EULA), shrink wrap contract, clickwrap, Fair Use, Fair Dealing and DMCA.

It is, of course, legal to purchase a ROM image which has been licensed to you by the rights holder. For example, Atari once made a number of their original arcade games available in ROM format which is compatible with the MAME emulator through the online ROM retailer Star ROMs. Nintendo provides a service on their 7th generation console, the Wii, that allows players to purchase old games from various systems, such as the NES, which will download a ROM image and emulator upon purchase (see Virtual Console).

The vast majority of computer and video games from the history of such games are no longer manufactured. As such, the copyright holders of some games have offered free licenses to those games, often on the condition that they be used for non-commercial purposes only. For example, fourteen of the games emulated in MAME, including Gridlee and Robby Roto, have been made available under such licenses and are distributed by the MAME project.

While some games which no longer make any profit fit into the category above, the vast majority are no longer available in any form. The legality of obtaining such games varies from country to country. Some countries have special exceptions in copyright laws or case law which permit (or discourage less) copying when an item is not available for legal purchase or when the copying is for non-commercial or research purposes, while other countries may make such practises firmly illegal. There is often a distinction drawn between distribution and downloading, with distribution being seen as the greater offence.

Commercial distribution of copyrighted games without the consent of the copyright holder is generally illegal in almost all countries, with those who take part in such activities being liable for both criminal and civil penalties. Online auction sites such as eBay have sometimes been used by sellers to sell unauthorised copies of games which are advertised as legitimate copies. Such sellers, in addition to violating copyright laws, may also be prosecuted for fraud or false advertising.

There have been few convictions and lawsuits related to ROM trading. Criminal convictions tend to be related to high-profile warez groups which trade combinations of recent films and computer games. In contrast, the ROM scene tends to concentrate mostly on older games. Given the lack of continuing profit from most older games, the grievances of games companies rarely exceed sending a cease and desist letter which demands that the recipient stop distributing the copyrighted works in question.

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Motorola 68008

Motorola MC68008.

The Motorola 68008 is an 8/16/32-bit microprocessor made by Motorola. It is a version of the Motorola 68000 with an 8-bit external data bus, as well as a smaller address bus.

The original 68000 had a 24-bit address bus and a 16-bit data bus. These relatively large buses made it hard to design a low-cost system around the 68000; they were difficult to lay out on a circuit board and needed a lot of supporting circuitry. A 16-bit data bus also required twice as many memory chips as an 8-bit one.

The 68008, introduced in 1982, was designed to work with low-cost 8-bit memory systems. Because of its smaller data bus, it was only about half as fast as a 68000 of the same clock speed. However, it was still faster than competing 8-bit microprocessors, because the 68008's internal architecture was more powerful and efficient.

Except for its smaller data and address buses, the 68008 behaved identically to the 68000 and had the same internal organization and microarchitecture.

The 68008 was an HMOS chip with about 70000 transistors; it came in 8 and 10 MHz speed grades. There were two distinct versions of the chip. The original version came in a 48-pin dual in-line package and had a 20-bit address bus, allowing it to use up to 1 megabyte of memory. A later version came in a 52-pin plastic leaded chip carrier; this version provided a 22-bit address bus and could support 4 megabytes of memory.

Very few computer systems used the 68008 as the main processor; the Sinclair QL personal computer is the best known of these. However, the 68008 was popular in embedded systems.

Motorola ended production of the 68008 in 1996.

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DDR SDRAM

Corsair XMS DDR-400 Memory with Heat Spreaders

DDR SDRAM (double-data-rate synchronous dynamic random access memory) is a class of memory integrated circuits used in computers. It achieves nearly twice the bandwidth of the preceding "single data rate" SDRAM by double pumping (transferring data on the rising and falling edges of the clock signal) without increasing the clock frequency.

With data being transferred 64 bits at a time, DDR SDRAM gives a transfer rate of (memory bus clock rate) × 2 (for dual rate) × 64 (number of bits transferred) / 8 (number of bits/byte). Thus with a bus frequency of 100 MHz, DDR SDRAM gives a maximum transfer rate of 1600 MB/s.

JEDEC has set standards for data rates of DDR SDRAM, divided into two parts: The first specification is for memory chips and the second is for memory modules. As DDR SDRAM is superseded by the newer DDR2 SDRAM, the older DDR version is sometimes referred to as DDR1 SDRAM.

Note: All above listed are specified by JEDEC as JESD79. All RAM data rates in-between or above these listed specifications are not standardized by JEDEC — often they are simply manufacturer optimizations using higher-tolerance or overvolted chips.

The package sizes in which DDR SDRAM is manufactured are also standardized by JEDEC.

There is no architectural difference between DDR SDRAM designed for different clock frequencies, e.g. PC-1600 (designed to run at 100 MHz) and PC-2100 (designed to run at 133 MHz). The number simply designates the data rate that the chip is guaranteed to run at, hence DDR SDRAM is guaranteed to run at lower and can possibly run at higher clock rates than those for which it was made. These practices are known as "underclocking" and "overclocking" respectively.

DDR SDRAM for desktop computers DIMMs have 184 pins (as opposed to 168 pins on SDRAM, or 240 pins on DDR2 SDRAM), and can be differentiated from SDRAM DIMMs by the number of notches (DDR SDRAM has one, SDRAM has two). DDR for notebook computers SO-DIMMs have 200 pins which is the same number of pins as DDR2 SO-DIMMs. These two specifications are notched very similarly and care must be taken during insertion when you are unsure of a correct match. DDR SDRAM operates at a voltage of 2.5 V, compared to 3.3 V for SDRAM. This can significantly reduce power consumption. Chips and modules with DDR-400/PC-3200 standard have a nominal voltage of 2.6 Volt.

Many new chipsets use these memory types in dual-channel configurations, which doubles or quadruples the effective bandwidth.

Module and chip characteristics are inherently linked.

Total module capacity is a product of one chip's capacity by the number of chips. ECC modules multiply it by 8/9 because they use one bit per byte for error correction. A module of any particular size can therefore be assembled either from 32 small chips (36 for ECC memory), or 16(18) or 8(9) bigger ones.

DDR memory bus width per channel is 64 bits (72 for ECC memory). Total module bit width is a product of bits per chip by number of chips. It also equals number of ranks (rows) multiplied by DDR memory bus width. Consequently a module with greater amount of chips or using x8 chips instead of x4 will have more ranks.

This example compares different real-world server memory modules with a common size of 1 GB. One should definitely be careful buying 1 GB memory modules, because all these variations can be sold under one price position without stating whether they are x4 or x8, single or dual ranked.

There is a common belief that number of module rows or ranks equals number of sides. As above data shows, this is not true. One can find (2-side, 1-rank) or (2-side, 4-rank) modules. One can even think of 1-side, 2-rank memory module having 16(18) chips on single side x8 each, but it's unlikely such a module was ever produced.

In this context High Density memory means non-ECC 184 pin SDRAM memory.

PC3200 is DDR SDRAM specified to operate at 200 MHz using DDR-400 chips with a bandwidth of 3,200 MB/s. As DDR stands for Double Data Rate this means that the effective clock rate of PC3200 memory is 400 MHz.

1 GB PC3200 non-ECC modules are usually made with 16 512 Mbits chips, 8 down each side (512 Mbit x 16 chips) / (8 bits (per Byte)) = 1024 MBytes. The individual chips making up a 1 GByte memory module are usually organized with 64M bits and a data width of 8 bits for each chip, commonly expressed as 64M x 8. Memory manufactured in this way is low density RAM and will usually be compatible with any motherboard specifying PC3200 DDR-400 memory.

In the context of the 1 GB non-ECC PC3200 SDRAM module there is very little visually to differentiate Low Density from High Density RAM. High Density DDR RAM modules will, like their Low Density counterparts, usually be double sided with eight 512 Mb chips per side. The difference is that each chip, instead of being organized in a 64M x 8 configuration is organized with 128M bits and a data width of 4 bits, or 128M x 4. To further confuse the issue, some RAM is labeled as 128M x 8, and is also called high density.

Most High Density PC3200 modules are assembled using Samsung chips. These chips come in both the familiar 22 x 10mm (approx) TSOP2 and smaller squarer 12 x 9mm (approx) FBGA package sizes. High density Samsung chips can be identified by the numbers on each chip. If the sixth and seventh characters are "04" (for example K4H510438D-UCCC) then the chips are x 4 and High Density. If the sixth and seventh characters are "08" then the chips are x 8 and Low Density.

High Density RAM devices were designed to be used in registered memory modules for servers. As a result, performance or response times may suffer when used on a desktop or workstation. JEDEC standards do not apply to high-density DDR RAM in desktop implementations. JEDEC's technical documentation however supports 128Mb X 4Mb semiconductors as such that contradicts 128X4 being classified as high density. As such "High Density" is a relative term which can be used to describe memory which is not supported by a particular motherboard's memory controller.

DDR (DDR1) has been superseded by DDR2 SDRAM, which has some modifications to allow higher clock frequency, but operates on the same principle as DDR. Competing with DDR2 are Rambus XDR DRAM. DDR2 has become the standard, as XDR is lacking support. DDR3 SDRAM is a new standard that offers even higher performance and new features.

DDR's prefetch buffer depth is 2 bits; DDR2 uses 4 bits. Although the effective clock rates of DDR2 are higher than for DDR, the overall performance was no greater in the early implementations, primarily due to the high latencies of the first DDR2 modules. DDR2 started to be effective by the end of 2004, as modules with lower latencies became available.

Memory manufacturers have stated that it is impractical to mass-produce DDR1 memory with effective clock rates in excess of 400 MHz. DDR2 picks up where DDR1 leaves off, and is available at clock rates of 400 MHz and higher.

RDRAM is a particularly expensive alternative to DDR SDRAM, and most manufacturers have dropped its support from their chipsets.

DDR1 memory's prices have substantially increased since Q2 2008 while DDR2 prices are reaching an all-time low. In January 2009, 1GiB DDR1 is 2-3 times more expensive than 1GiB DDR2.

MDDR is an acronym that some enterprises use for Mobile DDR SDRAM, a type of memory used in some portable electronic devices, like mobile phones, handhelds, and digital audio players. While standard DDR SDRAM operates at a voltage of 2.5 V, MDDR operates at voltage of 1.8 V, which allows a reduced power consumption.

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Powerchip Semiconductor

Powerchip Semiconductor (traditional Chinese: 力晶半導體; GTSM: 5346) is a maker of DRAM memory chips and other semiconductor chips. Powerchip also sells foundry services to other firms. The company was founded in 1994 at Hsinchu Science Park in Taiwan. It has four fabrication lines, three of which handle 300mm silicon wafers. According to iSuppli, an industry news and research service, Powerchip has 5 percent of the world market share in DRAM.

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Video memory

Video memory is a term generally used in computers to describe some form of writable memory, usually RAM, dedicated to the purpose of holding the information necessary for a graphics card to drive a display device. In modern 3D graphics cards, the video memory may also hold 3D vector data, textures, backbuffers, overlays and GPU programs.

This memory sometimes takes the form of dedicated memory chips integrated in the framebuffer, and sometimes takes the form of a Shared Memory Architecture (SMA).

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Source : Wikipedia